1. Field of the Invention
This invention relates to an output circuit, a digital/analog circuit and a display apparatus realized by using the same.
2. Description of the Related Art
Liquid crystal displays (LCDs) provides advantages of being thin and lightweight and operating at a low power consumption rate. Hence, they have recently been finding a variety of applications including display sections of portable telephone sets (mobile phones, cellular phones), PDA (personal digital assistants), notebook-sized personal computers and other mobile electronic appliances. Additionally, as a result of the technological advancement in the field of displaying moving scenes on large display screens of liquid crystal display apparatus in most recent years, stand type large screen liquid crystal display apparatus and large screen liquid crystal television sets have become available to say nothing of mobile applications. Many liquid crystal display apparatus are active matrix drive type apparatus that can operate as high definition display apparatus. Now, a typical configuration of active matrix drive type liquid crystal display apparatus will be briefly described by referring to FIG. 20 of the accompanying drawings. FIG. 20 schematically illustrates an equivalent circuit for certain principal components connected to a pixel of a liquid crystal display 1.
Generally, the display section 960 of an active matrix drive type comprises a semiconductor substrate formed by arranging transparent pixel electrodes 964 and thin film transistors (TFTs) 963 in the form of a matrix (having 1,280×3 pixel columns×1,024 pixel rows in the case of a color SXGA panel), an opposed substrate 966 on which a single transparent electrode 966 is formed and liquid crystal filled between the two oppositely disposed substrates.
The operation of turning on and off each of the TFTs 963 that function as switches is controlled by a scanning signal. More specifically, as a tone voltage that corresponds to a video signal is applied to one of the pixel electrodes 964 to turn on the corresponding TFT 963, the transmittance of the liquid crystal there is changed due to the potential difference produced between the pixel electrode 964 and the opposed substrate electrode 966 and the potential difference is maintained by a corresponding liquid crystal capacity 965 for a predetermined period of time to display an image there.
A plurality of data lines 962 for transmitting a plurality of level voltages (tone voltages) to be applied to the pixel electrodes 964 and a plurality of scanning lines 961 for transmitting scanning signals are arranged on the semiconductor substrate to form a lattice (1,280×3 data lines and 1,024 scanning lines in the case of a color SXGA panel). Thus, the scanning lines 961 and the data lines 962 operate as large capacitive load due to the capacity that arises at each of intersections of two lines, the liquid crystal capacity sandwiched between the semiconductor substrate and the opposed substrate electrode and other factors.
Scanning signals are supplied to the scanning lines 961 by means of a gate driver 970, while a tone voltage is supplied to each of the pixel electrodes 964 by means of a data driver 980 by way of the data lines 962.
The operation of rewriting the data of a scene is performed in each frame period (1/60 seconds), during which the pixel rows (lines) are sequentially selected as scanning lines and tone voltages are supplied to the respective pixel electrodes by way of the data lines.
While the gate driver 970 is required only to supply at least binary scanning signals, the data driver 980 is required to drive the data lines by drive voltages of multi-valued level, the multi-value being a function of the number of data lines. Therefore, a differential amplifier that can highly precisely output voltages is used for the buffer section of the data driver 980.
High image quality liquid crystal display apparatus (with an increased number of colors) have been developed in recent years. Currently, there is an increasing demand for liquid crystal display apparatus that can display at least 260,000 colors (6-bit video data for each of RGB) and preferably 26,800,000 colors (8-bit video data for each of RGB).
Therefore, the data driver that outputs tone voltages that corresponds to such multi-bit video data required to highly precisely output voltages. Furthermore, as the number of elements of the circuit section for processing video data rises, the chip area of the data driver LSI increases to push up the manufacturing cost. Now, this problem will be discussed in detail below.
FIG. 21 of the accompanying drawings illustrates the configuration of the data driver 980 of FIG. 20. Some of the principal components of the data driver 980 are shown in blocks in FIG. 21. Referring to FIG. 21, the data driver 980 comprises a latch address selector 981, a latch 982, a tone voltage generating circuit 983, decoders 984 and buffer circuits 985.
The latch address selector 981 determines the timing of data latch according to clock signal CLK The latch 982 latches video digital data at the timing determined by the latch address selector 981 and outputs the data simultaneously to the decoders 984 according to STB signal (strobe signal). The tone voltage generating circuit 983 generates tone voltages for a number of different tones that correspond to the video data. The decoders 984 select one of the tone voltages corresponding to the input data and output it. The buffer circuits 985 receive the tone voltages output respectively from the corresponding decoders 984 and amplify the electric currents thereof, which are then output from them as output voltages Vout.
For example, when 6-bit video data are input, the number of tones is 64 and the tone voltage generating circuit 983 generates tone voltages of 64 different levels. Then, the decoder 984 is designed to select one of the tone voltages of 64 levels.
When, on the other hand, 8-bit video data are input, the number of tones is 256 and the tone voltage generating circuit 983 generates tone voltages of 256 different levels. Then, the decoder 984 is designed to select one of the tone voltages of 256 levels.
Thus, as the number of bits increases for video data, the circuit size of the tone voltage generating circuit 983 and that of the decoders 984 increase. When the number of bits of each video data is raised from 6 to 8, the circuit size is expanded by four times. Therefore, the chip area of the data driver LSI increases remarkably as the number of bits of each video data rises to consequently push up the manufacturing cost.
To cope with this problem, techniques have been proposed to suppress the increase of the chip area of the data driver LSI if the number of bits rises. For example, U.S. Pat. No. 6,246,351 (Patent Document 1) describes such a technique. FIG. 22 of the accompanying drawings schematically illustrates the circuit arrangement proposed in above-cited Patent Document 1 (and corresponds to FIG. 2 of Patent Document 1). Referring now to FIG. 22, it comprises a string DAC section (decoder section) 4001 that includes a string of a set of resistors R000 through R255 and a set of voltage selection switches S000 through S255 for selecting a voltage that are arranged at respective positions located between adjacent resistors and an interpolation amp section 4100 that includes switches 4004 for selectively receiving as input the voltages supplied to a differential amplifier having a plurality of homo-polar differential pairs and two input terminals 4002, 4003 to the non-inverting inputs of the differential amplifier.
The string DAC section 4001 selects the two voltages between the opposite ends of a resistor selected out of the resistors R000 through R255 of the resistor string by the switches S000 through S255 that are controlled by the upper M bits of a digital data and the selected voltages are supplied respectively to the input terminals 4002, 4003 of the interpolation amp section 4100. The two voltages selected by the switches are limited to the voltages at the opposite ends of one of the resistors R000 through R255 of the string of resistors and hence the voltages at the opposite ends of a plurality of serially connected resistors or same voltages would never be selected.
In the interpolation amp section 4100, the voltages V1, V2 supplied respectively to the input terminals 4002, 4003 are selectively input to non-inverting inputs 4111, 4121, 4131, 4141 by means of the switches 4004 that are controlled by the lower N bits of the digital data so that it is possible to output the voltages that can internally divide the difference voltage between the voltages V1 and V2 to appropriate ratios that correspond to the ratios of the numbers of different inputs of V1 and V2. Since four differential pairs are provided in FIG. 22, it is possible to output four voltages including three voltages that internally divides the difference voltage between the two voltages V1, V2 of the terminals 4002, 4003 to ratios 1:3, 1:1 and 3:1 and V1, using the LSB (least significant bit). Thus, it is possible to reduce the number of levels of the voltage to be input relative to the number of levels of the voltage to be output to 1/(number of differential pairs). Therefore, it is possible to reduce the number of power supply lines and the area of the string DAC section.
U.S. Pat. No. 5,396,245 (Patent Document 2) describes another technique. FIG. 23 of the accompanying drawings schematically illustrates the circuit arrangement proposed in above-cited Patent Document 2 (and corresponds to FIG. 5 of Patent Document 2). Referring now to FIG. 23, the interpolation amp section 4100b slightly differs from the interpolation amp section 4100 of Patent Document 1 in terms of configuration. For example, while the four differential pairs are driven by so many different electric current sources in the arrangement of FIG. 22, the four differential pairs are driven by a single common electric current source 4200b in the arrangement of FIG. 23.
The arrangement of FIG. 23 is identical with that of FIG. 22 in that two voltages are selected from a string of resistors R000b through R255b by means of switches S000b through S255b and the input to the differential amplifier 4100b is controlled by means of switches 4004b to internally divide the difference voltage between V1 and V2 to output corresponding voltages. Thus, the arrangement of FIG. 23 also provides the advantage of reducing the number of input power supply lines. The fact that the two voltages selected by the switches are limited to the voltages at the opposite ends of one of the resistors R000b through R255b of the string of resistors is also common to the arrangement of FIG. 22 and that of FIG. 23.
ECL multi-valued logic circuits comprising two differential pairs respectively having bases adapted to receive input signals, collectors connected to a common load resistance and emitters commonly connected to each other so as to be driven by electric current sources having different electric current values and an output transistor for driving the output terminals, using one of the terminals of the load circuit as input (see, inter alia, JP-A-61-248619).
When applying any of the above known arrangements to a multi-output driver such as the data driver of a display apparatus, it is important to minimize the area of the differential amplifier. When any of the known arrangement described above by referring to FIGS. 22 and 23 is used for the data driver, while it is possible to reduce the size of the part of decoders, the number of differential pairs has to be increased to two, four, eight, . . . on in order to reduce the number of tone power source lines by ½, ¼, ⅛, . . . . Then, the area occupied by the differential amplifier is increased to a very large extent to lose the area-saving effect.